1. Field of the Invention
This present invention relates to a memory protection technology, and it particularly relates to a method and a circuit for individually specifying attributes on access by address ranges.
2. Description of the Related Art
Microprocessors and other data processing apparatuses execute access for read, write and so forth by issuing addresses to a memory or other devices (hereinafter referred to simply as a xe2x80x9cdevicexe2x80x9d) in the logical address space. Depending on the addresses, logical regions may often be defined where read and write are both permitted, where only read may be permitted, or where neither read nor write is permitted. These characteristics concerning access (hereinafter referred to as xe2x80x9caccess attributesxe2x80x9d or simply as xe2x80x9cattributesxe2x80x9d) may sometimes be set in units of logical regions called xe2x80x9cpages,xe2x80x9d for instance. To prohibit or restrict the rewrite or read of data of a device by setting attributes is generally called protection.
One example of a memory protection circuit in which attributes are individually specified by address ranges can be found in U.S. Pat. No. 6,021,476. In this circuit according to the U.S. patent, each of address ranges for a plurality of logical regions can be specified, and priority is fixedly predetermined for each of the logical regions. And when an address issued by a microprocessor is contained in an address range for a plurality of logical regions, the logical region with the highest priority (hereinafter referred to as xe2x80x9cthe highest priority regionxe2x80x9d also) is selected, and access is executed in accordance with the attributes determined for the logical region.
For example, where 4 KB of operating system (hereinafter described as xe2x80x9cOSxe2x80x9d) program region and 12 KB of user program region are mapped into a 16 KB RAM, a region of 16 KB is, in general, first divided into four regions of 4 KB each, and then one of them is assigned to the xe2x80x9cOS program regionxe2x80x9d and the remaining three to the xe2x80x9cuser program region.xe2x80x9d This requires at least four times of setting operations. In the case of the above-mentioned U.S. patent, however, the purpose is attained if the whole region of 16 KB is mapped into the xe2x80x9cuser program regionxe2x80x9d and then the 4 KB portion of it only is mapped to overlap in the xe2x80x9cOS program regionxe2x80x9d and the priority for this 4 KB is set higher. This requires the defining of two regions only, thus making the setting simpler.
However, the inventor has come to realize that because of fixed priorities given to the logical regions in the above-mentioned patent, there is room for improvement in the setting change following the change of memory map. For instance, consider a case where the attributes for a 30 KB logical region containing addresses 0xffff8000 (0xffff8000 indicates ffff8000 in the hexadecimal notation; hereinafter, xe2x80x9c0xxe2x80x9d represents hexadecimal in the similar manner) to 0xfffff7ff are full access, which means both readable and writable, and cacheable, and the attributes for a 2 KB logical region containing addresses 0xfffff800 to 0xffffffff are read only and cacheable. In the case of the above-mentioned U.S. patent, when the priorities are fixed in advance as
logical region 0 less than logical region 1 less than logical region 2, that is, when logical region 2 is fixed as the highest priority region, the setting is made as:
For Logical Region 0:
The address range is 32 KB from 0xffff8000 to 0xffffffff.
The attributes are full access and cacheable.
For Logical Region 1:
The address range is 2 KB from 0xfffff800 to 0xffffffff.
The attributes are read only and cacheable.
Here, consider a case of a change of memory map in which the attributes for 6 KB only of the 30 KB full-access and cacheable logical region are changed to read-only and uncacheable. Then the setting will be made as:
For Logical Region 0:
The address range is 32 KB from 0xffff8000 to 0xffffffff.
The attributes are full access and cacheable.
For Logical Region 1:
The address range is 8 KB from 0xffffe000 to 0xffffffff.
The attributes are read only and uncacheable.
For Logical Region 2:
The address range is 2 KB from 0xfffff800 to 0xffffffff.
The attributes are read only and cacheable.
Here, the 2 KB logical region, which was read only and cacheable before the change of memory map, retains the same address range and the same attributes of read only and cacheable even after the change of memory map, but, for that logical region, the address range and attributes set for logical region 1 before the memory map change must be changed to the setting for logical region 2. Thus, where a memory protection circuit is set by the program of a microprocessor, the changing of the program is complex and therefore requires an extremely careful work.
Moreover, where memory is protected by dynamically changing the attributes by a program, it is naturally desired that there be fewer processing steps for the setting change.
The present invention has been made in view of foregoing problems, and an object thereof is to make simpler the modification of the program necessary to change the setting of a memory protection circuit or to reduce the number of processing steps required for the setting change.
A preferred embodiment according to the present invention relates to a memory protection circuit which controls access, in a logical address space, to a device from a data processing apparatus such as a microprocessor. This circuit comprises: an address range register unit which respectively specifies address ranges of a plurality of logical regions in the logical address space; an attribute register unit which specifies an access attribute for each of the logical regions; an address comparison unit which judges whether or not an access request address for the device is contained in each of the logical regions; a priority register unit which specifies priority of access for each of the logical regions; an attribute determining unit, when there is a logical region or more which is judged as containing the access request address, which specifies and outputs an attribute specified for a logical region whose priority is highest among the logical regions; and a register setting unit which is capable of repeatedly setting the address range register unit, the attribute register unit and the priority register unit.
Representative of the xe2x80x9cdevicexe2x80x9d is a memory as mentioned earlier. Yet it is not necessary for the device to be memory as long as it is accessible via logical address space similar to memory map. For example, the device may be a memory-mapped I/O device. Moreover, optional devices, the appearance of which is indistinguishable between memory and I/O device, such as various extended bus cards, are xe2x80x9cdevicesxe2x80x9d as long as at least part of them is mapped into a logical address space.
Similarly, the xe2x80x9cmemory protection circuitxe2x80x9d does not necessarily have memory as its target of protection, but is a general term for circuits that protect arbitrary devices mapped to the logical address space in the same way as the memory mapped thereto.
Since this circuit can set the priorities of the logical regions variably and repeatedly, the setting change of address range and attributes necessitated by the setting change of protection becomes simple.
This circuit may further include a protection error unit which outputs a protection error signal when none of the logical regions is judged to contain the access request address or when an access attribute for the access request address is not of permitting nature. This structure may be realized by, for example, a gate element which outputs the protection error signal as active when, for example, all of comparison results by the address comparison unit indicate xe2x80x9cnot containedxe2x80x9d.
This circuit may further include a unit which outputs a protection error signal when the access attribute for the access request address indicates xe2x80x9caccess prohibitedxe2x80x9d. As an example, the protection error signal is outputted in a case where the attribute of an access request address is xe2x80x9cread onlyxe2x80x9d while the data processing apparatus is activating write operation for the access request address.
This circuit may further include a selection unit which selects a predetermined access attribute when none of the logical regions is judged to contain the access request address. Such access will be, for example, xe2x80x9cno access (both read and write are prohibited)xe2x80x9d. Specifically speaking, there may be provided a default attribute register unit which sets an attribute in a case when none of the logical regions is judged to contain the access request address, and a register setting unit which is capable of repeatedly setting said default attribute register unit.
Another preferred embodiment according to the present invention relates also to a memory protection circuit which controls access, in a logical address space, to a device from a data processing apparatus. This circuit includes: an address range register unit which sets address ranges of a plurality of logical regions in the logical address space in a manner that overlapping is permitted; and a priority register unit which specifies access priority for each of the plurality of logical regions so that the access priority can be reset externally. In this structure, when an access request address to the device is simultaneously contained in the plurality of logical regions, a logical region whose priority is highest is selected as an access destination.
Still another preferred embodiment according to the present invention relates to a memory protection method. This method includes: setting address ranges of a plurality of logical regions in a logical address space in a manner that overlapping is permitted; when an access request address is simultaneously contained in the plurality of logical regions, determining a logical region whose priority is highest by referring to priorities of the logical regions; identifying an access attribute of the logical region whose priority was determined highest; generating access according to the identified access attribute; and resetting, as appropriate, the priorities in each of the plurality of logical regions.
Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be sub-combination of these described features.